1. Field of the Invention
The invention relates to a detector for a receiver, which at the same time produces a clock phase detection signal for identification of a clock phase, and a carrier phase detection signal for identification of a carrier phase, of a received signal which is received by the receiver.
2. Description of the Prior Art
FIG. 1 shows an arrangement according to the prior art. A transmitter with an internal data source sends a modulated transmission signal via a transmission channel to a receiver. The receiver is generally a free-running receiver, that is to say it does not receive any separate synchronization signals from the transmitter, but determines the clock and carrier phase from the received signal.
FIG. 2 shows a transmitter according to the prior art, as is illustrated in FIG. 1. The transmitter contains a data or bit source, which emits a data bit stream to a mapping unit. The mapping unit in each case maps a plurality of data items in the data bit stream onto a complex data symbol. For example, one data symbol comprises two bits. In this case, by way of example, the first bit of the data symbol determines the real part (I) and the second bit determines the imaginary part (Q) of the data symbol to be transmitted. A modulator modulates a cosinusoidal carrier signal, which is at a carrier frequency fc (C: carrier) onto the real part (I). This is done by multiplying the real part by the carrier signal. In the same way, the imaginary part (Q) is multiplied by a sinusoidal carrier signal, which is likewise at the carrier frequency (fc). An adder adds the modulated real part and the modulated imaginary part, and applies the sum signal to a pulse shaping filter within the transmitter. The pulse shaping filter matches the transmission signal to the transmission channel.
The stream of data symbols emitted from the data source is at a specific clock frequency or symbol frequency fT. For data symbol detection, the receiver must identify the phase of the carrier signal, and the clock phase. The clock frequency or symbol frequency at which the data source emits the data symbols is generally known to the receiver. Conventional receivers according to the prior art have a first control loop for carrier synchronization, and a second control loop for clock synchronization to the received signal. The control loop for carrier synchronization includes a carrier phase detector, which determines the discrepancy from a desired, predetermined nominal carrier phase. The control loop for clock synchronization includes a clock phase detector, which determines the discrepancy from a desired predetermined clock phase.
Carrier phase detectors are conventionally subdivided into two different groups, specifically into the group of so-called DD carrier phase detectors, and into the group of so-called NDA carrier phase detectors. In the case of synchronization of the receiver to the carrier signal, the carrier phase and the carrier frequency of the modulated received signal are not known in advance. The phase discrepancy between the received signal and the desired nominal phase is calculated for carrier synchronization by the carrier phase detector by means of a carrier phase loop, which forms a control loop.
FIG. 3 shows the calculated feedback signal for a DD carrier phase detector according to the prior art on the complex plane, with the x axis representing the real part of the received data symbol, and the y axis representing the imaginary part of the received data symbol. The DD carrier phase detector according to the prior art weights the input data symbols linearly as follows:D=−Re Sign(Im)+Im·Sign(Re)  (1)
The darker the shading in FIG. 3, the more negative is the value of the feedback signal D emitted from the DD carrier phase detector.
By way of example, the situation for the following four received data symbols E1 is shown in the following table:
TABLE 1E1E2E3E4Re11.10.11.9Im10.91.90.1D0−0.2+1.8−1.8
If the received data symbol is located in the upper left-hand corner of the first quadrant of the complex plane (for example E3=(0.1; 1.9), the value of the emitted feedback signal D has a high positive value (for example D3=+1.8).
If the received data symbol is in the right-hand lower corner of the first quadrant of the complex plane (for example E4=(1.9; 0.1), a high negative value is emitted from the carrier phase detector as the feedback signal (D4=−1.8).
Four equidistant nominal data symbols are defined for a 4 PSK-modulated signal, for example:Enom1=(+1; +1);Enom2=(−1; +1)Enom3=(−1; −1)Enom4=(+1; −1)
In this case, the four (m=4) different nominal data symbols Enom are located in the four different quadrants (I-IV) of the complex plane, as illustrated in FIG. 3.
In the example illustrated in FIG. 3, the nominal phase for the four nominal data symbols is Enom=45°.
The DD carrier phase detector calculates the feedback signal D for each received data symbol, which has a nominal phase of φ=45° for D=0.
One disadvantage of DD detectors according to the prior art is that the calculation of the Equation (1) which corresponds to the feedback signal D involves a hard transition occurring between the individual decisions. A light region with a high positive feedback signal value and a dark region with a relatively high negative feedback signal value D are located immediately alongside one another, as can be seen from FIG. 3. When the feedback signal value D has a high positive value of, for example, +1.8, the carrier phase loop rotates in the clockwise sense, while the carrier phase loop rotates in the anticlockwise sense when the feedback signal value has a high negative value of, for example, D=−1.8.
In the case of the DD carrier phase detector according to the prior art and as illustrated in FIG. 3, those received data symbols which are located at the boundary between the phases of two nominal data symbols are more strongly weighted than received data symbols which are located in the vicinity of the nominal phase of φ=45°. For example, the received data symbols E3, E4, which have a relatively phase discrepancy with respect to the nominal received data symbol Enom1=(1; 1) lead to a feedback signal D with a large amplitude, specifically D3=+1.8 and D4=−1.8. In contrast, a received data symbol which has a relatively small phase discrepancy with respect to the nominal data symbol (Enom=1.1)), specifically the received data symbol E2=(1.1; 0.9), leads to a feedback signal value of D=−0.2, that is to say the amplitude of the feedback signal of a received data symbol which has a relatively small phase discrepancy with respect to the nominal received data symbol is less than the amplitude of the feedback signal D for a received data symbol which has a relatively high phase discrepancy between it and the nominal data symbol. Now, however, particularly those received data symbols which have a relatively high phase discrepancy with respect to a nominal data symbol are in fact relatively unreliable. For example, a received data symbol E=(1, 0) has the same phase discrepancy with respect to the nominal data symbol in the first quadrant (Enom=(1, 1)) and with respect to the nominal data symbol in the fourth quadrant (Enom4=(1, −1)). The probability of a received data symbol Enom which is located precisely on the boundary corresponding to the first nominal data symbol Enom1 or to the fourth received data symbol is 50%. The DD phase carrier detector according to the prior art and as shown in FIG. 3 thus does not take account of the reliability probability of the received data symbol, and the variance of the signal amplitudes of the feedback signal D, which is calculated by the DD carrier phase detector according to the prior art, is relatively high. In a corresponding manner, the power gain of the downstream digital loop filter must be reduced, so that the stabilization times of a carrier phase loop which uses a DD carrier phase detector according to the prior art and as shown in FIG. 3 are relatively long. In the event of a rapid change in the received signal, the receiver is thus not able to quickly follow the signal, so that the bit error rate rises.
FIG. 4 shows, on the complex plane, a feedback signal D which is calculated by an NDA carrier phase detector according to the prior art. An NDA carrier phase detector such as this is described, for example, by A. J. Viterbi and A. M. Viterbi “non linear estimation of PSK-modulated carrier phase with application to burst digital transmission” in IEEE TransInfoTheory Vol. IT-32, pages 543-551 (July 1983). The feedback signal D for Q PSK and 4 PSK is calculated using the following equation:
                    D        =                                                            r                x                            ·                              Mod                ⁢                                                                  [                                                                            Arg                      (                                                                        (                                                      Re                            +                                                          j                              ·                              Im                                                                                )                                                4                                            )                                        +                                          2                      ⁢                      π                                                        ,                                      2                    ⁢                    π                                                  ]                                      -            π                    2                                    (        2        )            where, in principle, x is freely variable, but x is normally set to be equal to 0, so that:r=√{square root over (Re2+Im2)}=1  (3)
The following values are obtained for the digital feedback signal D for four examples of received data symbols E1-E4 with an NDA carrier phase detector such as this:
TABLE 2E1E2E3E4Re11.10.11.9Im10.91.90.1D0−0.199+1.466−1.466
The NDA carrier phase detector according to the prior art and as illustrated in FIG. 4 has the same disadvantage as that already mentioned with the conventional DD detector according to the prior art as shown in FIG. 1, however, that there is a hard transition between the individual decisions.
Owing to the high signal variance of the calculated feedback signal D, the stabilization behavior of a carrier phase loop which has an NDA carrier phase detector such as this is relatively poor. This means that the carrier phase loop stabilizes only slowly, since the loop gain of the downstream digital loop filter must be set to be relatively low.
Conventional receivers have two separate circuits for carrier synchronization and for clock synchronization, that is to say a first control loop is provided for carrier synchronization with a carrier phase detector, and a second loop is provided for clock synchronization with a clock phase detector contained in it. In this case, the clock phase is determined first, followed by the carrier phase, sequentially. Once the clock phase has been determined, that is to say once the correct sampling time is known, the carrier phase is then determined in conventional receivers. In order to determine the clock and carrier phase, the transmitter sends a training sequence, which is known to the receiver, via the transmission channel. The sequential determination of the clock phase and of the carrier phase within the receiver has the serious disadvantage, however, that respectively half and only a portion of the entire signal length of the training sequence is in each case available for determination of the clock phase and for determination of the carrier phase. However, the training sequence that is emitted from the transmitter has only a relatively short signal length. In consequence, the variance in the estimation of the clock phase and in the estimation of the carrier phase in the receiver is very high. Because of the relatively inaccurate estimate of the carrier phase and of the clock phase, the subsequent control process in the receiver is relatively inaccurate, so that the error rate for detection of the received data symbols rises.
A further disadvantage of the separate control loops for carrier synchronization and for clock synchronization is that two separate detectors must be provided within the receiver, specifically one detector for identification of the carrier phase and one detector for identification of the clock phase. The circuitry complexity or overhead within the receiver is thus relatively high.
European patent EP 451 289 B1 describes a detector for a receiver for production of a clock phase detection signal and of a carrier phase detection signal as a function of a plurality of clock polyphase signals from an oversampled received signal. The detector has a plurality of carrier phase detectors, to each of which a clock polyphase signal is applied, and which determine a carrier phase of the respectively applied clock polyphase signal. The detector furthermore contains means for determination of the clock phase of the data emitted by the carrier phase detectors.